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7 lines
1.4 KiB
7 lines
1.4 KiB
\select@language {english}
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\contentsline {figure}{\numberline {1\tmspace +\thinmuskip {.1667em}--\tmspace +\thinmuskip {.1667em}1}{\ignorespaces The block diagram of the Atheros AR9331 SoC used as a main processing unit on GL.inet board\relax }}{4}{figure.caption.11}
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\contentsline {figure}{\numberline {1\tmspace +\thinmuskip {.1667em}--\tmspace +\thinmuskip {.1667em}2}{\ignorespaces The front side of the GL.inet board exposing the main Atheros SoC, RAM and interfaces\relax }}{5}{figure.caption.12}
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\contentsline {figure}{\numberline {1\tmspace +\thinmuskip {.1667em}--\tmspace +\thinmuskip {.1667em}3}{\ignorespaces The back side of the GL.inet board exposing the Flash memory and a main voltage regulator\relax }}{6}{figure.caption.13}
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\contentsline {figure}{\numberline {2\tmspace +\thinmuskip {.1667em}--\tmspace +\thinmuskip {.1667em}1}{\ignorespaces Toto je \IeC {\v s}tvorec\relax }}{7}{figure.caption.14}
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\contentsline {figure}{\numberline {2\tmspace +\thinmuskip {.1667em}--\tmspace +\thinmuskip {.1667em}2}{\ignorespaces Grafick\IeC {\'e} zobrazenie rie\IeC {\v s}enia rovnice \ref {r:1}\relax }}{8}{figure.caption.16}
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\contentsline {figure}{\numberline {3\tmspace +\thinmuskip {.1667em}--\tmspace +\thinmuskip {.1667em}1}{\ignorespaces Teplotn\IeC {\'a} z\IeC {\'a}vislos\IeC {\v t}\/ spinovo-mrie\IeC {\v z}kov\IeC {\'e}ho relaxa\IeC {\v c}n\IeC {\'e}ho \IeC {\v c}asu\relax }}{9}{figure.caption.17}
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