GL-inet router board images replaced with the custom ones, without the

blueprint
master
Peter Babič 9 years ago
parent 960724b803
commit 44ae1e8916
  1. BIN
      figures/gl-inet_pcb_down.jpg
  2. BIN
      figures/gl-inet_pcb_up.jpg
  3. 24
      problemexpres.tex
  4. BIN
      tukethesis.pdf

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figures/gl-inet_pcb_down.jpg (Stored with Git LFS)

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figures/gl-inet_pcb_up.jpg (Stored with Git LFS)

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@ -145,18 +145,18 @@ TP-Link TL-WR703N \gls{router} is a popular choice among \gls{hw} customisation
Whole printed circuit board of TL-WR703N was remade by the GL.inet team to expose the unused \gls{gpio} pins on the \gls{soc}, utilize two \Gls{ethernet} port instead of one and utilize the \gls{usb} 2.0 port. Memory chips were replaced by their higher capacity alternatives.
\begin{figure}[ht!]
\centering
\includegraphics[width=.8\textwidth,angle=0]{gl-inet_pcb_up}
\caption{The front side of the GL.inet board exposing the main Atheros \gls{soc}, \gls{ram} and \glspl{interface}}\label{f:board_front}
\end{figure}
\begin{figure}[ht!]
\centering
\includegraphics[width=.8\textwidth,angle=0]{gl-inet_pcb_down}
\caption{The back side of the GL.inet board exposing the \Gls{flash} memory and a main voltage regulator}\label{f:board_back}
\end{figure}
%\begin{figure}[ht!]
%\centering
%\includegraphics[width=.8\textwidth,angle=0]{gl-inet_pcb_up}
%\caption{The front side of the GL.inet board exposing the main Atheros \gls{soc}, \gls{ram} and \glspl{interface}}\label{f:board_front}
%\end{figure}
%
%
%\begin{figure}[ht!]
%\centering
%\includegraphics[width=.8\textwidth,angle=0]{gl-inet_pcb_down}
%\caption{The back side of the GL.inet board exposing the \Gls{flash} memory and a main voltage regulator}\label{f:board_back}
%\end{figure}

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tukethesis.pdf (Stored with Git LFS)

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